1. Field of the Invention
The present invention is related to processing systems and processors, and more specifically to techniques for predicting load-hit-store hazards at dispatch times to reduce rejection of dispatched load instructions.
2. Description of Related Art
In pipelined processors supporting out-of-order execution (OOE), overlaps between store and load instructions causing load-hit-store hazards represent a serious bottleneck in the data flow between the load store unit (LSU) and the instruction dispatch unit (IDU). In particular, in a typical pipelined processor, when a load-hit-store hazard is detected by the LSU, the load instruction that is dependent on the result of the store instruction is rejected, generally several times, and reissues the load instruction along with flushing all newer instructions following the load instruction. The above-described reject and reissue operation not only consumes resources of the load-store data path(s) within the processor, but can also consume issue queue space in the load-store execution path(s) by filling the load-store issue queue with rejected load instructions that must be reissued. When such an LHS hazard occurs in a program loop, the reject and reissue operation can lead to a dramatic reduction in system performance.
In some systems, the reissued load instruction entries are tagged with dependency flags, so that subsequent reissues will only occur after the store operation on which the load instruction depends, preventing recurrence of the reissue operations. However, rejection of the first issue of the load instruction and the consequent flushing of newer instructions still represents a significant performance penalty in OOE processors.
It would therefore be desirable to provide a processor and a method for managing load-store operations with reduced rejection and reissue of operations, in particular load rejections due to load-hit-store hazards.